1. Technical Field
The present invention is relates to a semiconductor device, and more particularly to a semiconductor device in which a device margin is reduced in an input/output protection section.
2. Description of the Related Art
Recently, the operation frequency of a semiconductor integrated circuit device has become very high. A wiring line region allocated for power supply wiring lines and ground wiring lines tends to have a greater increase in operation frequency. Therefore, it becomes easy for an internal circuit of the semiconductor integrated circuit device to be destroyed if a voltage surge is momentary applied or a high voltage is consistently applied when the semiconductor integrated circuit device is actually used. In order to avoid the destruction of the inner circuit due to application of the voltage or the high voltage, a protection circuit is conventionally connected with input/output terminals to improve the voltage endurance of the internal circuit. As one of such techniques, Japanese Laid Open Patent Application (JP-P2002-289704A) describes a technique, in which boron regions of different depths are formed as P-wells between two N-wells provided in a P-type substrate apart from each other. These regions are formed through two ion implantations using a same mask. The deeper boron region is deeper than the two N-wells to increase the breakdown voltage and to suppress leak between the two N-wells at the same time.
However, when the interval between the two N-wells is of order of submicron, it is not possible to keep the breakdown voltage between the two N-wells high in the P-well structure of the above Japanese Laid Open Patent Application (JP-P2002-289704A).
In conjunction with the above description, a semiconductor device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 5-267606). In the semiconductor device of this conventional example, a semiconductor substrate of a first conductive type is provided. An embedded layer of a second conductive type opposite to the first conductive type is formed inside the semiconductor substrate over the whole of the semiconductor substrate. A first well of the first conductive type extends from the semiconductor substrate surface into the inside. A wall region of the second conductive type is formed to surround the peripheral of the first well from the embedded layer to the semiconductor substrate surface. A second well of the first conductive type extends from the semiconductor substrate surface into the inside. A third well of the second conductive type extends from the semiconductor substrate surface into the inside, and is contact with the embedded layer.
Also, a semiconductor device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 6-5867). The semiconductor device of this conventional example is a power MOS transistor formed on a semiconductor substrate of a first conductive type. At lease two well diffusion layers of a second conductive type are provided for the semiconductor substrate to have a predetermined interval. A source region of the first conductive type is formed in the well diffusion layer, and a portion of the semiconductor substrate other than said well diffusion layers is formed as a drain region. A portion of the semiconductor substrate between the two well diffusion layers is of the first conductive type and impurity is doped in a higher concentration in a shallower portion of the semiconductor substrate. A cross section in a horizontal direction becomes larger in a depth direction.
Also, a semiconductor device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 2-148852). In the semiconductor device of this conventional example, a gate electrode is partially provided on a semiconductor substrate directly or via a gate insulating film. A drain region and a source region are provided on the gate electrode in the semiconductor substrate surface. An insulating film is provided in a wall region of the drain region other than a lower region below the drain region and a channel region below the gate electrode. An impurity dope region is provided at a predetermined depth straight below the gate electrode. This impunity dope region has the same conductive type as the semiconductor substrate and an impurity concentration higher than that of the semiconductor substrate. The peak impurity concentration position of the impurity dope region is within 0.8 μm from the semiconductor substrate surface.